Efficient VLSI Layout of Grid Pyramid Networks
نویسندگان
چکیده
Reducing the VLSI layout area of on-chip networks can result in lower costs and better performance. Those layouts that are more compact can result in shorter wires and therefore the signal propagation through the wires will take place in less time. The grid-pyramid network is a generalized pyramid network based on a general 2D Grid structure (such as mesh, torus, hypermesh or WK-recursive mesh). Such pyramid networks form a wide class of interconnection networks that possess rich topological properties. In this paper, we study these topologies from the VLSI-layout efficiency point of view. Also, we investigated on the layout of RTCC-pyramid networks that we believe can be considered in the class of Grid-pyramid networks.
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